Single and multiple silicon chip packages, or semiconductor chip packages, are used to provide electrical connection between semiconductor chips and other electronic components in an electronic circuit, such as die-to-package or chip-to-board interconnects. These single and multiple chip packages serve as a substrate to securely anchor electronic components and as a pathway for electrical signals.
Newer technologies, such as area array attachment techniques, are driving engineers to design chip packages that more closely match the coefficient of thermal expansion (CTE) of silicon, or otherwise ensure, the reliability of such packages through thermal cycling. Embracing, and in some cases over-riding, these trends is a constant drive in the electronics industry to improve performance and simultaneously reduce cost.
Most conventional single and multiple chip packages are typically constructed from thick, mechanically robust dielectric materials, such as ceramics (e.g., alumina, aluminum nitride, beryllium oxide, cordierite, and mullite) and reinforced organic laminates (e.g., epoxies with woven glass, polyimides with woven glass, and cyanate ester with woven glass). In some cases, materials are combined to produce certain improved properties, for example, a package may have a ceramic base with one or several thin films of polyimides or benzocyclobutane (BCB) disposed thereupon.
The most common single or multiple chip electronic packages are made from injection molded plastics with metal lead frames. Sometimes, these packages include laminated interconnect structures made from materials such as FR-4 and BT resins. Recently, advances have been made with these laminated structures to somewhat increase density and performance, as in the case of laminated ball grid array packages. Such packages employing FR-4 and BT resins have a number of advantages, such as lower cost, wide availability, lower dielectric constant, lower resistivity conduction paths, and lighter weight. Unfortunately, these packages suffer from a multiplicity of shortcomings which detract from their usefulness. These shortcomings include low wiring densities, low via densities, high via capacitance, poor CTE match to silicon, non-flatness, large package size, poor thermal stability, poor thermal conduction, and thick packages. Some of these deficiencies have been addressed with the use of thin film polyimides and/or BCBs on ceramics. These materials have high via and wiring densities, small size, and lower dielectric constant. Despite these advantages, these materials still suffer from many shortcomings including high cost, highly resistive conduction paths, lower characteristic impedance, and processing problems leading to limited manufacturing sources and long lead times.
In an attempt to address the industry need for superior price-performance in single and multiple chip packages, packaging technologies have been developed which are based on thin dielectrics that are not reinforced with glass fibers or other mechanical aids. Examples of these thin dielectrics include thin polyimides and polytetrafluoroethylene (PTFE) based dielectrics, such as ceramic filled PTFE or cyanate ester impregnated porous PTFE. Compared with the conventional materials described hereinabove, these packaging technologies yield superior via and wiring density, extremely low dielectric constants, lower via capacitance, lower resistance, smaller package size, thinner packages, CTE matching over a wide range, lower package weight, greater thermal stability, and higher reliability than competing technologies. In some cases, thin dielectrics are used that contain reinforcing materials such as woven glass. Notwithstanding such advantages, these technologies are impaired by very thin, fragile packages. For example, while typical ceramic packaging has a modulus of elasticity values of 40-50.times.10.sup.6 psi, a typical modulus for a ceramic filled PTFE based package is only about 100,000 psi. Due to these constraints, packaging made from this material is very difficult to handle and assemble. Mechanical stiffeners are commonly added to thin packages made with these materials to give them the needed mechanical robustness.
However, a shortcoming in previous methods to attach the stiffener to the substrate may have resulted when the substrate and stiffener were not properly aligned. This may have created problems during the downstream chip assembly process such as improper edge registry. Another shortcoming in previous methods may have resulted when the stiffener was not properly adhered to the substrate. This may have also created problems during the downstream chip assembly process, which typically utilizes high temperatures, such as partial delamination of the stiffener from the substrate. The result may have been an adverse effect in thermal and electrical conductance. Also, long term reliability of the chip may have been effected due to temperature cycling.
The foregoing illustrates limitations that may exist in present electronic chip package methods. Thus, it is apparent that it would be advantageous to provide an improved method and apparatus for aligning and laminating stiffeners to substrates directed at overcoming one or more of the limitations set forth above. Accordingly, a suitable alternative is provided including features more fully disclosed hereinafter.